» Intel® AVX: New Frontiers In Performance Improvements And Energy Efficiency
  An overview of the new instructions and capabilities of the Intel® AVX along with a brief background on Instruction Set Architecture (ISA)(PDF)
» Intel® Advanced Vector Extensions Programming Reference
» Intel® AVX Realization of IIR Filter for Complex Float Data
» Intel® AVX Realization of Lanczos Interpolation in Intel IPP 2D Resize Transform
» Optimize for Intel® AVX Using Intel® Math Kernel Library’s Basic Linear Algebra Subprograms (BLAS) with DGEMM Routine
» Advanced Encryption Standard (AES) Instructions Set
» Carry-Less Multiplication and Its Usage for Computing The GCM Mode
Intel SSE4.2
  Intel® SSE4.2 is a new subset of Intel® SSE4 instructions that will be introduced in the 45nm Next Generation Intel® Core™2 processor family (Nehalem). These techniques are used to enhance Intel® XML Software performance through tighter integration with the AVX platform.
» Schema Validation with Intel® Streaming SIMD Extensions 4 (Intel® SSE4)
» XML Parsing Accelerator with Intel® Streaming SIMD Extensions 4 (Intel® SSE4)
» Intel® XML Software Suite

Intel® AVX (Intel® Advanced Vector Extensions) is a 256 bit instruction set extension to SSE and is designed for applications that are floating point intensive.

The enhancement in Intel® AVX allow for improved performance due to wider vectors, new extensible syntax, and rich functionality including the ability to better manage, rearrage and sort data.
Intel announced Intel® AVX at the Spring Intel Developer Forum in April 2008 to share the plans and start working with global developers prior to the 2010 release. Intel® AVX will be a part of the platforms ranging from notebooks to servers.
Please take a moment to download the technical paper and join the forum to discuss Intel® AVX with other developers and engineers.